In the semiconductor industry, an increasing number of chip designs are being developed that mix silicon-on-insulator (SOI) technology with bulk Si technology. For example, it is known to provide a Si wafer that includes logic devices located in an SOI region, while forming a dynamic random access memory device in a bulk region. Hybrid substrates containing these various regions that are functionalized for a specific device offer the best of several technology worlds. In a hybrid substrate including, for example, an SOI region and a bulk region, the SOI region offers higher performance, lower power consumption and better electrostatic discharge protection for logic devices, while the bulk Si provides advantages for the memory devices such as the absence of the SOI floating body effect which can introduce bias dependent threshold voltage shifts.
In the prior art, a hybrid substrate including an SOI like region and a bulk-like region are formed utilizing a patterned SIMOX (Separation by IMplantation of OXygen) process in which a patterned mask is first formed atop a surface of a Si-containing substrate. Oxygen ions are then implanted into the substrate through an opening provided in the patterned mask. The masked oxygen ion implantation step creates a discrete and isolated damaged region within the Si-containing substrate. An annealing step is then performed which causes the formation of a discrete and isolated buried oxide (BOX), i.e., SIMOX island.
A structure produced by the prior art process mentioned above is shown, for example, in FIG. 1. As shown, the mixing of a SIMOX island with bulk can create defects, particularly Si fractures, due to volume mismatch as the edges of the SIMOX island.
Co-assigned U.S. Pat. No. 6,333,532 to Davari, et al. disclose a method and structure for forming patterned SOI regions and bulk regions in the same single crystal Si-containing substrate. In one embodiment of the '532 patent, a trench can be formed through the buried oxide ends to remove high concentrations of dislocations in the single crystal Si-containing substrate. This is shown, for example, in FIG. 8 of the '532 patent. In this prior art method, there is no guarantee that for a given trench width that it will cover all of the defects because the defects are formed randomly with random lengths.
In addition to substrates containing SOI regions and bulk regions, substrates that include a heterostructure (including a plurality of heterostructure layers) with SOI regions and/or bulk regions, are highly desirable. As was the case mentioned above, hybrid substrates including heterostructure layers which induce strain can create threading defects that propagate horizontally before rising to the surface. The propagation of the threading defect may damage adjacent devices. A prior art structure including heterostructure layers is shown, for example, in FIG. 2.
In view of the above, there is a need for providing hybrid substrates that avoid the aforementioned problems with prior art hybrid substrates. In particular, there is a need for providing a hybrid substrate that includes a structure that is capable of preventing propagation of lattice stress from another structure that generates the lattice stress.